CS6303 CA Syllabus Computer Architecture Syllabus – CSE 3rd SEM Anna University

Anna University Regulation 2013 Computer Science & Engineering (CSE) CS6303 CA Syllabus for all 5 units are provided below. Download link for CSE 3rd SEM CS6303 Computer Architecture Syllabus is listed down for students to make perfect utilization and score maximum marks with our study materials.

Anna University Regulation 2013 Computer Science & Engineering (CSE) 3rd SEM CS6303 CA-Computer Architecture Syllabus

CS6303     COMPUTER ARCHITECTURE     L T P C 3 0 0 3

OBJECTIVES:

  •  To make students understand the basic structure and operation of digital computer.
  •  To understand the hardware-software interface.
  •  To familiarise the students with arithmetic and logic unit and implementation of fixed point and floating-point arithmetic operations.
  •  To expose the students to the concept of pipe-lining.
  •  To familiarise the students with hierarchical memory system including cache memories and virtual memory.
  •  To expose the students with different ways of communicating with I/O devices and standard I/O interfaces.

UNIT I OVERVIEW & INSTRUCTIONS

Eight ideas – Components of a computer system – Technology – Performance – Power wall – Uniprocessors to multiprocessors; Instructions – operations and operands – representing instructions – Logical operations – control operations – Addressing and addressing modes.

UNIT II ARITHMETIC OPERATIONS

ALU – Addition and subtraction – Multiplication – Division – Floating Point operations – Subword parallelism.

UNIT III PROCESSOR AND CONTROL UNIT

Basic MIPS implementation – Building datapath – Control Implementation scheme – Pipelining – Pipelined datapath and control – Handling Data hazards & Control hazards – Exceptions.

UNIT IV PARALLELISM

Instruction-level-parallelism – Parallel processing challenges – Flynn’s classification – Hardware multithreading – Multicore processors

UNIT V MEMORY AND I/O SYSTEMS

Memory hierarchy – Memory technologies – Cache basics – Measuring and improving cache performance – Virtual memory, TLBs – Input/output system, programmed I/O, DMA and interrupts, I/O processors.

TOTAL: 45 PERIODS

OUTCOMES:

At the end of the course, the student should be able to:

  •  Design arithmetic and logic unit.
  •  Design and anlayse pipelined control units
  •  Evaluate performance of memory systems.
  •  Understand parallel processing architectures.

TEXT BOOK:

1. David A. Patterson and John L. Hennessey, “Computer organization and design‟, Morgan Kauffman / Elsevier, Fifth edition, 2014.

REFERENCES:

1. V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, “Computer Organisation“, VI th edition, Mc Graw-Hill Inc, 2012.

2. William Stallings “Computer Organization and Architecture” , Seventh Edition , Pearson Education, 2006.

3. Vincent P. Heuring, Harry F. Jordan, “Computer System Architecture”, Second Edition, Pearson Education, 2005.

4. Govindarajalu, “Computer Architecture and Organization, Design Principles and Applications”, first edition, Tata McGraw Hill, New Delhi, 2005.

5. John P. Hayes, “Computer Architecture and Organization”, Third Edition, Tata Mc Graw Hill, 1998.

6. http://nptel.ac.in/.

If you require any other notes/study materials, you can comment in the below section.

Related Links

For CS6303 CA Previous Year Question Papers – Click here

For CS6303 CA Question Bank/2marks 16marks with answers – Click here

For CS6303 CA Important Questions/Answer Key – Click here

For CS6303 CA Lecture Notes – Click here

Search Terms

Anna University 3rd SEM CSE CA Syllabus

CS6303 Computer Architecture Syllabus free download

Anna University CSE CA Syllabus Regulation 2013

CS6303 Syllabus, CA Unit wise Syllabus – CSE 3rd Semester

Comments

comments

Leave a Reply

sai
Scroll To Top
Copy Protected by Chetan's WP-Copyprotect.