### CS6201 DPSD Question Papers

Anna University Regulation 2013 Computer Science & Engineering (CSE) CS6201 DPSD Question Papers for all 5 units are provided below. Download link for CSE 2nd SEM CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN Previous Year Question Papers are listed down for students to make perfect utilisation and score maximum marks with our study materials.

Anna University Regulation 2013 Computer Science & Engineering (CSE) 2nd SEM

CS6201CA-DIGITAL PRINCIPLES AND SYSTEM DESIGN Question paper

PART A – (10 X 2 = 20 Marks)

1. Represent the decimal numbers -200 & 200 using

2’s complement binary form. 2. Write the truth table of AND and XOR gates.

3. Draw the schematic of half adder logic.

4. Write the HDL descriptor of following circuit.

5. Determine the size & number of multiplexers required to implement the full adder.

6. Determine the no of address lines required for 512 bytes of memory and for 2kb memory.

7. Write state transition diagram of JK Flip-flop.

8. Draw the timing diagram showing the output of a 2 stage synchronous counter with respect to its clock signal.

9. Explain the next state characteristics of D and SR flip-flops.

10. Define static and dynamic hazards.

PART B-(5 X 16 = 80 Marks)

11. (a) (i) Convert (1947)10 into its equivalent octal and decimal representation (10)

(ii) Perform (147-89) using 2’s complement binary arithmetic. (6)

(Or)

(b) (i) Minimize the following expressions using K-Map Y= A’BC’D’ + A’BC’D + ABC’D’ + AB’C’D +A’B’CD’. (10)

(ii) State and prove De Morgan’s theorems (6)

12. (a) (i) Design a combinational circuit that comprises only of NOR gates for the following expression giving the input & output relation. Y=ABC + AC +B ‘ C (10)

(ii) Draw the schematic of full adder and give its truth table. (6)

(Or)

(b) (i)Design a BCD to Excess-3 code converter using truth table & K-Map simplification. (10) `

(ii) Draw the schematic of a magnitude comparator and give its truth table. 6)

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