CS6303 CA Question Papers
Anna University Regulation 2013 Electronic Communications Engineering ECE CS6303 CA old Question Papers for previous years are provided below. Download link for ECE 6th SEM CS6303 COMPUTER ARCHITECTURE Previous Year Question Papers are listed down for students to make perfect utilization and score maximum marks with our study materials.
Anna University Regulation 2013 Electronic Communications Engineering ECE
6th SEM CS6303 CA Question Papers
Previous Year Question Papers
1. Define word length.
- What are the merits and demerits of single address instructions?
- List the advantages of multibus organization.
- What are the inputs for hardwired control?
- What is the role of cache in pipelining?
- What would be the effect, if we increase the number of pipelining stages?
- What is DDR SDRAM?
- What is TLB?
- What are the components of an I/O interface?
PART B — (5 16 = 80 marks)
(ii) Define addressing mode and explain the basic addressing modes with an example for each.
(b)State and explain the rules in arithmetic operations on
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Anna University 6th SEM ECE CA Question Papers with answers
CS6303 COMPUTER ARCHITECTURE previous year question papers free download
Anna University ECE CA old question papers Regulation 2013
CS6303 Question Papers with answers, CA previous year question bank – ECE 6th Semester