EC6612 VLSI DESIGN (VLSI ) Lab Manual
Anna University Regulation 2013 Electronic Communications Engineering (ECE) EC6612 VLSI DESIGN (VLSI ) LAB Manual for all experiments is provided below. Download link for ECE 6th SEM EC6612 VLSI DESIGN (VLSI ) Laboratory Manual is listed down for students to make perfect utilization and score maximum marks with our study materials.
Anna University Regulation 2013 Electronic Communications Engineering (ECE)
6th SEM EC6612 VLSI DESIGN (VLSI ) LAB Manual
1. HDL based design entry and simulation of simple counters, state machines, adders (min 8 bit) and multipliers (4 bit min).
2. Synthesis, P&R and post P&R simulation of the components simulated in (I)above. Critical paths and static timing analysis results to be identified. Identify and verify possible conditions under which the blocks will fail to work correctly.
3. Hardware fusing and testing of each of the blocks simulated in (I). Use of either chip scope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the PLL and demonstrate the use of the PLL module for clock generation in FPGAs.
IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR GRAPHICS / EQUIVALENT)
4. Design and simulation of a simple 5 transistor differential amplifier.
Measure gain, ICMR, and CMRR
5. Layout generation, parasitic extraction and re simulation of the circuit designed (I)
6. Synthesis and Standard cell based design of an circuits simulated in 1(I) above. Identification of critical paths, power consumption.
7. For expt (c) above, P&R, power and clock routing, and post P&R
simulation.
8. Analysis of results of static timing analysis.
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SL.NO
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EXPERIMENTS
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1.
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SIMULATION FOR BASIC GATES USING XILINX
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2.
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SIMULATION FOR HALFADDER USING XILINX
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3.
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SIMULATION FOR FULL ADDER USING XILINX
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4.
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SIMULATION FOR MUX AND DEMUX USING XILINX
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5.
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SIMULATION FOR DECODER USING XILINX
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6.
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SIMULATION FOR ENCODER USING XILINX
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7.
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SIMULATION FOR PRBS GENERATOR USING XILINX
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8.
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SIMULATION FOR ACCUMULATOR USING XILINX
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9.
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SIMULATION FOR D FLIP FLOPS USING XILINX
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10.
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SIMULATION FOR JK FLIP FLOPS USING XILINX
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11.
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SIMULATION FOR SR FLIP FLOPS USING XILINX
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12.
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SIMULATION FOR CMOS INVERTER USING XILINX
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13.
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DESIGN FOR DIFFERENTIAL AMPLIFIER USING TANNER
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14.
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DESIGN FOR CMOS LAYOUT USING TANNER
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15.
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DESIGN FOR VOLTAGE CONTROLLED OSCILLSTOR USING TANNER
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16.
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DESIGN FOR COUNTERS USING TANNER
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17.
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DESIGN FOR UP AND DOWN COUNTERS USING TANNER
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EC6612 VLSI DESIGN (VLSI ) Lab Manual with all experiments – Download Here
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