EC8095 VLSI D Question Papers
Anna University Regulation 2017 ECE EC8095 VLSI D Question Papers for previous years are provided below. Previous Year Question Papers for ECE 6th SEM EC8095 VLSI Design, Engineering are listed down for students to make perfect utilization and score maximum marks with our study materials.
Anna University Regulation 2017 (ECE) 6th SEM EC8095 VLSI D – VLSI Design question paper
1.What is the need for demarcation line?
2.Compare NMOS and PMOS transistor.
3.State propagation delay of CMOS inverter.
4.Mention the different types of scaling principle.
5.Why NMOS device conducts strong zero and weak one?
6.Describe the lambda based design rules used for layout.
7.Demonstrate the stick diagram with an example.
8.Explain the hot carrier effect.
9.Draw the DC transfer characteristics of CMOS inverter.
10.Name the different operating modes of transistor?
11.Classify SPICE models for MOS transistor.
12.Outline the steps involved in IC fabrication?
13.Discuss the limitations of the constant voltage scaling.
14.Define body effect and write the threshold equation including the body effect.
15.Design a 3 input NAND gate.
16.List out second order effects of MOS transistor.
17.Determine whether an NMOS transistor with a threshold voltage of 0.7v is operating in the saturation region if GSV=2v and DSV=3v.
18.Summarize the equation for describing the channel length modulation effect in NMOS transistor.
19.Justify the tunneling current is higher for NMOS transistors than PMOS transistors with silica gate?
20.Consider the NMOS transistor in 180nm process with a nominal threshold voltage of 0.4v and doping level of 8x1017cm-3. Propose the body voltage.
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