EC8392 DE Important Questions, Digital Electronics Answer Key


EC8392 DE Important Questions

Anna University Regulation 2017 ECE EC8392 DE Important Questions with Answer Key and 3rd SEM EC8392 Digital Electronics Engineering Answer Key is listed down for students to make perfect utilization and score maximum marks with our study materials.



1. State De-Morgan’s theorem and mention its use.

2. Express the function C BAY  in canonical POS.

3. Convert the given decimal numbers to their binary equivalent 108.364, 268.025.

4. Why totem pole outputs cannot be connected together?

5. Simplify the following Boolean expression into one literal. W’X(Z’+YZ) + X(W+Y’Z).

6. Convert (115)10 and (235)10 into hexadecimal numbers.

7. Define ‘Minterm’ and ‘ Maxterm’.

8. Draw an active high tri-state Gate & write its truth table.

9. Show how to connect NAND gates to get an AND gate and OR gate?

10. State Distributive law and Duality principle.

11. What is meant by Prime Implicant and Essential prime implicants?

12. Find the minimized Boolean expression of this function F=XY+X(Y+Z) +Y(Y+Z).

13. Implement the given function using NAND gates only. F(X, Y, Z) = ) 6,0(m .

14. Find the canonical POS form of Y= A+B’C

15. If A & B are Boolean variables and if A=1 & B A =0, determine B?

16. Apply De-Morgan’s theorem to simplify C BA


1. (i)Find the Minimized logic function using K-Maps and Realize using NAND and NOR gate. F (A, B, C, D) =  ) 13,2()15,11,9,8,5,3,1( dm . (8)

(ii)Show that if all the gate in a two-level OR-AND gate network are replaced by NOR gate, the output function does not change. (5)

2. (i) Illustrate the MSOP representation for F(A,B,C,D,E) = m(1,4,6,10,20,22,24,26)+d(0,11,16,27) using K-map method. Draw the circuit of the minimal expression using only NAND gates. (7)

(ii) Write about Excess 3 and Gray Code with an example. (6)

3. (i) Develop the given function Y (M, N, O, P, Q) = ) 31,29,25,23,21,13,9,6,4,2,0( m . Draw the K-map and Implement the simplified expression using basic gates. (8)

(ii) Implement F= A’B’D’+ B’C’+E’ using NAND gates. (5)

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