EE6301 DLC Question Papers
Anna University Regulation 2013 EEE EE6301 DLC Question Papers for previous years are provided below. Previous Year Question Papers for EEE 3rd SEM EE6301 Digital Logic Circuits are listed down for students to make perfect utilization and score maximum marks with our study materials.
Anna University Regulation 2013 Electrical & Electronics Engineering (EEE) 3rd SEM EE6301 DLC -Digital Logic Circuits Syllabus
EE6301 DIGITAL LOGIC CIRCUITS LT P C 3 1 0 4
• To study various number systems , simplify the logical expressions using Boolean functions
• To study implementation of combinational circuits
• To design various synchronous and asynchronous circuits.
• To introduce asynchronous sequential circuits and PLCs
• To introduce digital simulation for development of application oriented logic circuits.
UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES 9
Review of number systems, binary codes, error detection and correction codes (Parity and Hamming code0- Digital Logic Families ,comparison of RTL, DTL, TTL, ECL and MOS families -operation, characteristics of digital logic family.
UNIT II COMBINATIONAL CIRCUITS 9
Combinational logic – representation of logic functions-SOP and POS forms, K-map representationsminimization using K maps – simplification and implementation of combinational logic – multiplexers and demultiplexers – code converters, adders, subtractors.
UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS 9
Sequential logic- SR, JK, D and T flip flops – level triggering and edge triggering – counters – asynchronous and synchronous type – Modulo counters – Shift registers – design of synchronous sequential circuits – Moore and Melay models- Counters, state diagram; state reduction; state assignment.
UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABLE LOGIC DEVICES 9
Asynchronous sequential logic circuits-Transition table, flow table-race conditions, hazards &errors in digital circuits; analysis of asynchronous sequential logic circuits-introduction to Programmable Logic Devices: PROM – PLA –PAL.
UNIT V VHDL 9
RTL Design – combinational logic – Sequential circuit – Operators – Introduction to Packages – Subprograms – Test bench. (Simulation /Tutorial Examples: adders, counters, flipflops, FSM, Multiplexers /Demultiplexers).
TOTAL (L:45+T:15): 60 PERIODS
• Ability to understand and analyse, linear and digital electronic circuits.
1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson Education 2nd edition, 2007.
2. M. Morris Mano, ‘Digital Design with an introduction to the VHDL’, Pearson Education, 2013.
3. Comer “Digital Logic & State Machine Design, Oxford, 2012.
1. Mandal ”Digital Electronics Principles & Application, McGraw Hill Edu,2013.
2. William Keitz, Digital Electronics-A Practical Approach with VHDL,Pearson,2013.
3. Floyd and Jain, ‘Digital Fundamentals’, 8th edition, Pearson Education, 2003.
4. Anand Kumar, Fundamentals of Digital Circuits,PHI,2013.
5. Charles H.Roth,Jr,Lizy Lizy Kurian John, ‘Digital System Design using VHDL, Cengage, 2013.
6. John M.Yarbrough, ‘Digital Logic, Application & Design’, Thomson, 2002.
7. Gaganpreet Kaur, VHDL Basics to Programming, Pearson, 2013.
8. Botros, HDL Programming Fundamental, VHDL& Verilog, Cengage, 2013.
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EE6301 DLC Question Papers
Anna University 3rd SEM EEE DLC Question Papers with answers
EE6301 Digital Logic Circuits previous year question papers free download
Anna University EEE DLC old question papers Regulation 2013
EE6301 Question Papers with answers, DLC previous year question bank – EEE 3rd Semester